Disk-drives contain a signal-processing chip, often referred to as a “read channel chip,” that converts the noisy analog signal from the magnetic recording head into the binary data sequence that is used by the host computer. A major component in a read channel chip is the channel detector. Extremely high-speed read channel chips are required to operate at data rates on the order of 3 GHz. Read channel chips for disk-drives that are used in portable lap-top computers and other battery-operated consumer electronics must be low-power. Since power usage increases with chip area and clock-speed, a good way to achieve low-power and high-throughput is to reduce the clock-rate and process more than one bit at a time with low-complexity signal processing that does not require significant area. Unfortunately, very complex area intensive signal processing is typically required to achieve the bit-error rate requirements for disk-drives.
The analog signal is filtered with an anti-aliasing filter and sampled so that there is one sample per bit. Because the bits are packed very tightly to achieve high storage capacity on the magnetic disk, the received samples have a low signal-to-noise ratio and are typically corrupted by inter-symbol-interference. The channel detector unravels the inter-symbol-interference by representing each possible combination of binary interfering symbols as states in a trellis. Typically, a 16-state trellis with four inter-symbol-interference symbols is required to provide sufficient performance in the channel detector. The area and power of the channel detector increase with the number of states in the trellis.
The binary sequences stored on the disk-drive are typically encoded with parity codes or error-correction codes that require soft-decisions from the channel detector to decode the sequence with sufficiently low error-rates. There are two main types of soft-output channel detectors. The most common type is a SOYA detector that uses a soft-output Viterbi algorithm (SOVA) to find the path through the trellis with the maximum probability given the received samples, and to calculate a soft-output for each bit along the path. A SOVA detector typically uses a forward state processor, a path memory, and a soft-output processor. Improved performance can be obtained by a maximum-a-posteriori (MAP) detector that uses a forward state processor, a backward state processor, and a soft-output processor. Since the backward state processor makes the MAP detector more complex than a SOVA detector, MAP detectors are not typically used. MAP detectors only provide small performance improvements over SOVA detectors and typically require larger chip area and more power. A MAP detector determines which binary value at each bit position has the maximum probability given the received samples, y. For each bit, a MAP detector calculates a log-likelihood ratio, which is the conditional probability that ck is equal to binary zero (0) divided by the conditional probability that ck is equal to binary one (1), given the received samples, as follows:Pr(ck=0|y)/Pr(ck=1|y).
In a Log-MAP detector, the soft-decision is the natural log of the likelihood ratio, and the hard-decision is the sign of the soft-decision. In a Max-Log-Map detector, the soft-decision is the natural log of the probability associated with the maximum probability path with ck=0 minus the natural log of the probability associated with the maximum probability path with ck=1. The Max-Log Map algorithm is a simplification of the Log-Map algorithm, and the difference in performance is typically small.
A MAP detector comprises a forward detector, a current branch metric detector, and a backward detector. A full-rate forward detector calculates forward state metrics leading to each of the states at time k−1. In most conventional designs, the backward detector calculates backward state metrics starting from a single state with state metric 0 at time k+Q (where Q is the backward detection period) and leading to each of the states at time k, in the backward direction. Another approach is to let all the states at time k+Q have state metrics equal to 0. In a full-rate MAP detector, the current branch step represents the state transitions from time k−1 to time k. In conventional designs, the number of states at time k and k−1 are typically the same. The current bit label ck is the bit for which the detector is currently calculating a sort-output. The soft-output at time k is generated from combined metrics that are calculated by adding together a forward state metric, a backward state metric and a current branch metric.
In order to keep up with the throughput of emerging magnetic disk drives, a need exists for a high-speed, low-power, high-performance soft-output channel detector. A MAP detector that is smaller than a SOYA detector when implemented at very high-speed, and has better performance is the ideal solution.